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Corey AshfordTheRealMDoerr
Corey Ashford
authored and
TheRealMDoerr
committedNov 11, 2020
8248188: Add IntrinsicCandidate and API for Base64 decoding
8248188: Add IntrinsicCandidate and API for Base64 decoding, add Power64LE intrinsic implementation. This patch set encompasses the following commits: Adds a new intrinsic candidate to the java.lang.Base64 class - decodeBlock(), and provides a flexible API for the intrinsic. The API is similar to the existing encodeBlock intrinsic. Adds the code in HotSpot to check and martial the new intrinsic's arguments to the arch-specific intrinsic implementation. Adds a Power64LE-specific implementation of the decodeBlock intrinsic. Adds a JMH microbenchmark for both Base64 encoding and encoding. Enhances the JTReg hotspot intrinsic "TestBase64.java" regression test to more fully test both decoding and encoding. Reviewed-by: rriggs, mdoerr, kvn
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‎src/hotspot/cpu/ppc/assembler_ppc.hpp

+23
Original file line numberDiff line numberDiff line change
@@ -338,6 +338,7 @@ class Assembler : public AbstractAssembler {
338338
MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
339339
MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
340340
MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
341+
MCRXRX_OPCODE = (31u << OPCODE_SHIFT | 576u << 1),
341342
SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1),
342343

343344
// condition register logic instructions
@@ -519,6 +520,8 @@ class Assembler : public AbstractAssembler {
519520
LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
520521

521522
// Vector-Scalar (VSX) instruction support.
523+
LXV_OPCODE = (61u << OPCODE_SHIFT | 1u ),
524+
STXV_OPCODE = (61u << OPCODE_SHIFT | 5u ),
522525
LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
523526
STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
524527
MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
@@ -530,12 +533,16 @@ class Assembler : public AbstractAssembler {
530533
XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3),
531534
XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3),
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XXSPLTW_OPCODE = (60u << OPCODE_SHIFT | 164u << 2),
536+
XXLAND_OPCODE = (60u << OPCODE_SHIFT | 130u << 3),
533537
XXLOR_OPCODE = (60u << OPCODE_SHIFT | 146u << 3),
534538
XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3),
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XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3),
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XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
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XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
538542
XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
543+
XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3),
544+
XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4),
545+
XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1),
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XVDIVDP_OPCODE = (60u << OPCODE_SHIFT | 120u << 3),
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XVABSSP_OPCODE = (60u << OPCODE_SHIFT | 409u << 2),
541548
XVABSDP_OPCODE = (60u << OPCODE_SHIFT | 473u << 2),
@@ -592,6 +599,7 @@ class Assembler : public AbstractAssembler {
592599
VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ),
593600
VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ),
594601

602+
VPEXTD_OPCODE = (4u << OPCODE_SHIFT | 1421u ),
595603
VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ),
596604
VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ),
597605

@@ -1099,6 +1107,7 @@ class Assembler : public AbstractAssembler {
10991107
static int frs( int x) { return opp_u_field(x, 10, 6); }
11001108
static int frt( int x) { return opp_u_field(x, 10, 6); }
11011109
static int fxm( int x) { return opp_u_field(x, 19, 12); }
1110+
static int imm8( int x) { return opp_u_field(uimm(x, 8), 20, 13); }
11021111
static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); }
11031112
static int l14( int x) { return opp_u_field(x, 15, 14); }
11041113
static int l15( int x) { return opp_u_field(x, 15, 15); }
@@ -1165,14 +1174,20 @@ class Assembler : public AbstractAssembler {
11651174
// Support Vector-Scalar (VSX) instructions.
11661175
static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
11671176
static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
1177+
static int vsrc( int x) { return opp_u_field(x & 0x1F, 25, 21) | opp_u_field((x & 0x20) >> 5, 28, 28); }
11681178
static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
11691179
static int vsrt( int x) { return vsrs(x); }
11701180
static int vsdm( int x) { return opp_u_field(x, 23, 22); }
1181+
static int vsrs_dq( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 28, 28); }
1182+
static int vsrt_dq( int x) { return vsrs_dq(x); }
11711183

11721184
static int vsra( VectorSRegister r) { return vsra(r->encoding());}
11731185
static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
1186+
static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
11741187
static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
11751188
static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
1189+
static int vsrs_dq(VectorSRegister r) { return vsrs_dq(r->encoding());}
1190+
static int vsrt_dq(VectorSRegister r) { return vsrt_dq(r->encoding());}
11761191

11771192
static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
11781193
static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
@@ -1675,6 +1690,7 @@ class Assembler : public AbstractAssembler {
16751690
inline void mcrf( ConditionRegister crd, ConditionRegister cra);
16761691
inline void mtcr( Register s);
16771692
// >= Power9
1693+
inline void mcrxrx(ConditionRegister cra);
16781694
inline void setb( Register d, ConditionRegister cra);
16791695

16801696
// Special purpose registers
@@ -2119,6 +2135,7 @@ class Assembler : public AbstractAssembler {
21192135
inline void vspltish( VectorRegister d, int si5);
21202136
inline void vspltisw( VectorRegister d, int si5);
21212137
inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2138+
inline void vpextd( VectorRegister d, VectorRegister a, VectorRegister b);
21222139
inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
21232140
inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b);
21242141
inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4);
@@ -2235,6 +2252,8 @@ class Assembler : public AbstractAssembler {
22352252
inline void mfvscr( VectorRegister d);
22362253

22372254
// Vector-Scalar (VSX) instructions.
2255+
inline void lxv( VectorSRegister d, int si16, Register a);
2256+
inline void stxv( VectorSRegister d, int si16, Register a);
22382257
inline void lxvd2x( VectorSRegister d, Register a);
22392258
inline void lxvd2x( VectorSRegister d, Register a, Register b);
22402259
inline void stxvd2x( VectorSRegister d, Register a);
@@ -2243,6 +2262,7 @@ class Assembler : public AbstractAssembler {
22432262
inline void mfvrwz( Register a, VectorRegister d);
22442263
inline void mtvrd( VectorRegister d, Register a);
22452264
inline void mfvrd( Register a, VectorRegister d);
2265+
inline void xxperm( VectorSRegister d, VectorSRegister a, VectorSRegister b);
22462266
inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
22472267
inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
22482268
inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
@@ -2256,6 +2276,9 @@ class Assembler : public AbstractAssembler {
22562276
inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
22572277
inline void xxbrd( VectorSRegister d, VectorSRegister b);
22582278
inline void xxbrw( VectorSRegister d, VectorSRegister b);
2279+
inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b);
2280+
inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c);
2281+
inline void xxspltib( VectorSRegister d, int ui8);
22592282
inline void xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
22602283
inline void xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
22612284
inline void xvabssp( VectorSRegister d, VectorSRegister b);

‎src/hotspot/cpu/ppc/assembler_ppc.inline.hpp

+10
Original file line numberDiff line numberDiff line change
@@ -378,6 +378,9 @@ inline void Assembler::mfcr( Register d ) { emit_int32(MFCR_OPCODE | rt
378378
inline void Assembler::mcrf( ConditionRegister crd, ConditionRegister cra)
379379
{ emit_int32(MCRF_OPCODE | bf(crd) | bfa(cra)); }
380380
inline void Assembler::mtcr( Register s) { Assembler::mtcrf(0xff, s); }
381+
// Introduced in Power 9:
382+
inline void Assembler::mcrxrx(ConditionRegister cra)
383+
{ emit_int32(MCRXRX_OPCODE | bf(cra)); }
381384
inline void Assembler::setb(Register d, ConditionRegister cra)
382385
{ emit_int32(SETB_OPCODE | rt(d) | bfa(cra)); }
383386

@@ -776,6 +779,8 @@ inline void Assembler::lvsl( VectorRegister d, Register s1, Register s2) { emit
776779
inline void Assembler::lvsr( VectorRegister d, Register s1, Register s2) { emit_int32( LVSR_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }
777780

778781
// Vector-Scalar (VSX) instructions.
782+
inline void Assembler::lxv( VectorSRegister d, int ui16, Register a) { assert(is_aligned(ui16, 16), "displacement must be a multiple of 16"); emit_int32( LXV_OPCODE | vsrt_dq(d) | ra0mem(a) | uimm(ui16, 16)); }
783+
inline void Assembler::stxv( VectorSRegister d, int ui16, Register a) { assert(is_aligned(ui16, 16), "displacement must be a multiple of 16"); emit_int32( STXV_OPCODE | vsrs_dq(d) | ra0mem(a) | uimm(ui16, 16)); }
779784
inline void Assembler::lxvd2x( VectorSRegister d, Register s1) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
780785
inline void Assembler::lxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
781786
inline void Assembler::stxvd2x( VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrs(d) | ra(0) | rb(s1)); }
@@ -784,7 +789,9 @@ inline void Assembler::mtvsrd( VectorSRegister d, Register a) { e
784789
inline void Assembler::mfvsrd( Register d, VectorSRegister a) { emit_int32( MFVSRD_OPCODE | vsrs(a) | ra(d)); }
785790
inline void Assembler::mtvsrwz( VectorSRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d) | ra(a)); }
786791
inline void Assembler::mfvsrwz( Register d, VectorSRegister a) { emit_int32( MFVSRWZ_OPCODE | vsrs(a) | ra(d)); }
792+
inline void Assembler::xxspltib(VectorSRegister d, int ui8) { emit_int32( XXSPLTIB_OPCODE | vsrt(d) | imm8(ui8)); }
787793
inline void Assembler::xxspltw( VectorSRegister d, VectorSRegister b, int ui2) { emit_int32( XXSPLTW_OPCODE | vsrt(d) | vsrb(b) | xxsplt_uim(uimm(ui2,2))); }
794+
inline void Assembler::xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLAND_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
788795
inline void Assembler::xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLOR_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
789796
inline void Assembler::xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLXOR_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
790797
inline void Assembler::xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLEQV_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
@@ -817,9 +824,11 @@ inline void Assembler::mtvrd( VectorRegister d, Register a) { em
817824
inline void Assembler::mfvrd( Register a, VectorRegister d) { emit_int32( MFVSRD_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
818825
inline void Assembler::mtvrwz( VectorRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
819826
inline void Assembler::mfvrwz( Register a, VectorRegister d) { emit_int32( MFVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
827+
inline void Assembler::xxperm( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXPERM_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
820828
inline void Assembler::xxpermdi(VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm) { emit_int32( XXPERMDI_OPCODE | vsrt(d) | vsra(a) | vsrb(b) | vsdm(dm)); }
821829
inline void Assembler::xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
822830
inline void Assembler::xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
831+
inline void Assembler::xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c) { emit_int32( XXSEL_OPCODE | vsrt(d) | vsra(a) | vsrb(b) | vsrc(c)); }
823832

824833
// VSX Extended Mnemonics
825834
inline void Assembler::xxspltd( VectorSRegister d, VectorSRegister a, int x) { xxpermdi(d, a, a, x ? 3 : 0); }
@@ -860,6 +869,7 @@ inline void Assembler::vspltisb(VectorRegister d, int si5)
860869
inline void Assembler::vspltish(VectorRegister d, int si5) { emit_int32( VSPLTISH_OPCODE| vrt(d) | vsplti_sim(simm(si5,5))); }
861870
inline void Assembler::vspltisw(VectorRegister d, int si5) { emit_int32( VSPLTISW_OPCODE| vrt(d) | vsplti_sim(simm(si5,5))); }
862871
inline void Assembler::vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VPERM_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
872+
inline void Assembler::vpextd( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPEXTD_OPCODE| vrt(d) | vra(a) | vrb(b)); }
863873
inline void Assembler::vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c){ emit_int32( VSEL_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
864874
inline void Assembler::vsl( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VSL_OPCODE | vrt(d) | vra(a) | vrb(b)); }
865875
inline void Assembler::vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4) { emit_int32( VSLDOI_OPCODE| vrt(d) | vra(a) | vrb(b) | vsldoi_shb(uimm(ui4,4))); }

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