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8254826: Add reduction nodes implementation for Arm SVE #13

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8254826: Add reduction nodes implementation for Arm SVE #13

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bb23e7e
8254826: Add reduction nodes implementation for Arm SVE
dongbohe Oct 15, 2020
87d741f
fix style problems
dongbohe Oct 21, 2020
8cf45a1
remove redundant T_CHAR
dongbohe Oct 23, 2020
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54 changes: 24 additions & 30 deletions src/hotspot/cpu/aarch64/aarch64_sve.ad
View file
Original file line number Diff line number Diff line change
@@ -869,7 +869,7 @@ instruct vpopcountI(vReg dst, vReg src) %{

instruct reduce_addB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (AddReductionVI src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -889,8 +889,7 @@ instruct reduce_addB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_addS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT ||
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_CHAR)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (AddReductionVI src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -910,7 +909,7 @@ instruct reduce_addS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_addI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (AddReductionVI src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -928,7 +927,7 @@ instruct reduce_addI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (AddReductionVL src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -972,7 +971,7 @@ instruct reduce_addD(vRegD src1_dst, vReg src2) %{

instruct reduce_andB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (AndReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -992,8 +991,7 @@ instruct reduce_andB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_andS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT ||
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_CHAR)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (AndReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1013,7 +1011,7 @@ instruct reduce_andS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_andI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (AndReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1031,7 +1029,7 @@ instruct reduce_andI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_andL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (AndReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1051,7 +1049,7 @@ instruct reduce_andL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp) %{

instruct reduce_orB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (OrReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1071,8 +1069,7 @@ instruct reduce_orB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_orS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT ||
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_CHAR)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (OrReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1092,7 +1089,7 @@ instruct reduce_orS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_orI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (OrReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1110,7 +1107,7 @@ instruct reduce_orI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_orL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (OrReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1130,7 +1127,7 @@ instruct reduce_orL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp) %{

instruct reduce_eorB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (XorReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1150,8 +1147,7 @@ instruct reduce_eorB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_eorS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT ||
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_CHAR)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (XorReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1171,7 +1167,7 @@ instruct reduce_eorS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_eorI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (XorReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1189,7 +1185,7 @@ instruct reduce_eorI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{

instruct reduce_eorL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (XorReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -1209,7 +1205,7 @@ instruct reduce_eorL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp) %{

instruct reduce_maxB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MaxReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
@@ -1229,8 +1225,7 @@ instruct reduce_maxB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlag

instruct reduce_maxS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT ||
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_CHAR)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MaxReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
@@ -1250,7 +1245,7 @@ instruct reduce_maxS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlag

instruct reduce_maxI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (MaxReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
@@ -1270,7 +1265,7 @@ instruct reduce_maxI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlag

instruct reduce_maxL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (MaxReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
@@ -1324,7 +1319,7 @@ instruct reduce_maxD(vRegD dst, vRegD src1, vReg src2) %{

instruct reduce_minB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MinReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
@@ -1344,8 +1339,7 @@ instruct reduce_minB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlag

instruct reduce_minS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT ||
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_CHAR)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MinReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
@@ -1365,7 +1359,7 @@ instruct reduce_minS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlag

instruct reduce_minI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (MinReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
@@ -1385,7 +1379,7 @@ instruct reduce_minI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp, rFlag

instruct reduce_minL(iRegLNoSp dst, iRegL src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (MinReductionV src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
20 changes: 10 additions & 10 deletions src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
View file
Original file line number Diff line number Diff line change
@@ -536,7 +536,7 @@ dnl REDUCE_ADD_EXT(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
define(`REDUCE_ADD_EXT', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -559,7 +559,7 @@ dnl REDUCE_ADD(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
define(`REDUCE_ADD', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -603,7 +603,7 @@ dnl REDUCE_AND_EXT(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
define(`REDUCE_AND_EXT', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -626,7 +626,7 @@ dnl REDUCE_AND(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
define(`REDUCE_AND', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -653,7 +653,7 @@ dnl REDUCE_OR_EXT(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
define(`REDUCE_OR_EXT', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -676,7 +676,7 @@ dnl REDUCE_OR(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
define(`REDUCE_OR', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -703,7 +703,7 @@ dnl REDUCE_XOR_EXT(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
define(`REDUCE_XOR_EXT', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -726,7 +726,7 @@ dnl REDUCE_XOR(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
define(`REDUCE_XOR', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(SVE_COST);
@@ -753,7 +753,7 @@ dnl REDUCE_MAXMIN_EXT(insn_name, op_name, reg_dst, reg_src, size, elem_type, cmp
define(`REDUCE_MAXMIN_EXT', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);
@@ -776,7 +776,7 @@ dnl REDUCE_MAXMIN(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1,
define(`REDUCE_MAXMIN', `
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
ELEMENT_SHORT_CHAR($6, n->in(2)));
n->in(2)->bottom_type()->is_vect()->element_basic_type() == $6);
match(Set dst ($2 src1 src2));
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
ins_cost(SVE_COST);